`timescale  1ns/1ps

module tb_fifo();

glbl glbl();

reg  input_clk;
reg  rst_n;

initial fork begin      //25M
  #3;
  input_clk = 1;
  forever begin
    #20;
    input_clk = ~input_clk;
  end
end
join


wire  sys_clk;   
wire  sys_rst_n;   

//		Clock name	| Frequency 	| Phase shift
//		C0        	| 100.000000MHZ	| 0  DEG     
pll u_pll(
    .refclk   (input_clk ),
    .reset    (~rst_n    ),
    .extlock  (sys_rst_n ),
    .clk0_out (sys_clk   )
); 

reg  re;
wire [7:0] rd_data;
wire [10:0] rdusedw;

reg  [7:0] wr_data;
reg  we;

parameter   DATA_LEN    =   'd50;
reg [7:0] array[DATA_LEN-1:0];
integer i;

initial begin
    rst_n  <= 1'b0;  
    #10
    rst_n <= 1'b1;
    // $stop;
    
    array[0] = 8'haa;
    array[1] = 8'hff;
    array[2] = 8'h00;
    array[3] = 8'h06;
    array[4] = 8'h01;
    array[5] = 8'h01;
    array[6] = 8'h56;
end      

fifo fifo_inst(
   .clk        (sys_clk   ),
   .rst        (~sys_rst_n),

   .we         (we        ),         //写请求
   .di         (wr_data   ),         //写数据,8bit
   .full_flag  (full_flag ),

   .re         (re        ),         //读请求
   .do         (rd_data   ),         //数据读出,8bit
   .empty_flag (empty_flag),
   .rdusedw    (rdusedw   )
);


endmodule
